CMOS High Efficiency On-chip Power Management by John Hu

By John Hu

This e-book offers with the subject material of energy administration built-in circuit (IC) layout, or built-in energy electronics, as a reaction to the starting to be want for energy-efficient electronics. The authors introduce quite a few energy administration IC layout thoughts to construct destiny energy-efficient “green” electronics. The aim is to accomplish excessive potency, that's necessary to meet shoppers’ turning out to be desire for longer battery lives. the focal point is to review topologies amiable for complete on-chip implementation (few exterior elements) within the mainstream CMOS know-how, for you to lessen the actual measurement and the producing expense of the devices.

  • Describes a couple of strategies at circuits and platforms point that raise sleep-mode potency to extend the battery existence, with no sacrificing functionality parameters;
  • Enables readers to layout for compactness, which calls for fewer cumbersome exterior parts and circuit topologies that lend themselves simply to complete on-chip integration;
  • Offers insights on how the potency boosting innovations for strength administration IC designs paintings towards society’s quest for greater power efficiency.

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ACM Symp. Operating Syst. 502044 Royannez P, Mair H, Dahan F, Wagner M, Streeter M, Bouetel L, Blasquez J, Clasen H, Semino G, Dong J, Scott D, Pitts B, Raibaut C, Ko U (2005) 90nm low leakage SoC design techniques for wireless applications. In: IEEE ISSCC Dig. Tech. Papers, pp 138–589 Vol. 1493907 Salerno DC, Jordan MG (2006) Methods and circuits for programmable automatic burst mode control using average output current Singh H, Agarwal K, Sylvester D, Nowka K (2007) Enhanced leakage reduction techniques using intermediate strength power gating.

In conclusion, DC line regulation is determined by the tunable range of Req of the pass element, given the output current and voltage it has to maintain. The method to improve line regulation includes up sizing the pass element (increasing W/L), and increasing the DC loop gain. However, the analysis in the following sections would reveal that these methods would lead to increased parasitics, slower slew rate, and instability. This gives the first example of the various trade-offs involved in power management IC design as indicated in Sect.

Therefore, supply voltage VDD needs to be reduced together with frequency f in order to significantly reduce the energy consumed (Burd et al. 2000). Used together with a real-time work monitor and scheduler , this technique can provide the optimum supply voltages and clock frequencies such that all computing tasks and processing needs are completed “just in time”, thereby eliminating any slack period. A simple illustration of the principles of DVFS is shown in Fig. 2. Adaptive Voltage Scaling (AVS) is similar to DVFS, but serves as a fine tune, self-adaptive power management scheme.

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