By Boris Murmann
With the appearance of strong electronic sign processing in moveable digital purposes, we've seen a turning out to be, unhappy call for for energy effective, high-speed and high-resolution analog-to-digital converters (ADCs). whereas know-how scaling has ended in innovative earnings in electronic computing strength and effort potency, development in analog-to-digital conversion interfaces has been relatively gradual. Digitally Assisted Pipeline ADCs: conception and Implementation explores the chance to lessen ADC strength dissipation through leveraging electronic sign processing services in superb line built-in circuit expertise. The defined digitally assisted pipelined ADC makes use of a statistics-based approach id process as an permitting point to switch precision residue amplifiers with basic open-loop achieve levels.
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Additional info for Digitally Assisted Pipeline ADCs: Theory and Implementation
Var'VTH ¨¨ D ¸¸ var¨¨ © E ¹ © gm ¹ (3-12) Analog Input V refp V refn Preamp ... ... ... Encoder Comparator-Latch Figure 3-8. Flash ADC block diagram. Dig ita l Output SCALING ANALYSIS 27 Substituting (3-8) and (3-9) into (3-12), we obtain V VOS 2 1 ª 2 « AV TH AE2 Aeff « ¬ §I · ¨¨ D ¸¸ © gm ¹ 2 º », »¼ (3-13) where Aeff is the effective device area, W·L. 2 Speed Limitations The conversion speed of a flash ADC is limited mainly by the effective bandwidth of the preamp/comparator. Consider the simple model for preamplifier/comparator interface shown in Figure 3-9.
2V is expected . – Increased sensitivity to interconnect parasitics. The RC delay of wires has been scaling much slower than device delays . g. Copper) and improved circuit-level routing solutions have become necessary. Despite the challenges above, digital circuits are expected to benefit from scaling CMOS technology for at least another five years. Conservative estimates predict that the energy per logic transition will continue to drop until the channel length reaches about 40nm .
In the following survey, we will examine the rate of performance growth in ADCs. To capture and compare performance of ADCs, we use a set of commonly used figures of merit. The following section briefly discusses these quantities with respect to their origin and limitations. 1 ADC Figure of Merit Considerations The product of conversion bandwidth and number of effective quantization levels represents the most basic performance metric for ADCs . 76dB . 02dB (2-2) Since the signal-to-noise and distortion ratio (SNDR) of a converter usually depends on the frequency of the input signal, this figure of merit must include some fixed condition for the frequency at which ENOB was measured.